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| author |   aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-13 09:34:48 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-13 09:34:48 +0000 |
| commit | 66896cb803b4865c0c35b218dbc407e1fcf7f7f7 (patch) | |
| tree | 63c1a7a79b7614ef91d0d431e14f32687b88f2f2 /target-arm | |
| parent | Fix regression introduced by r6824 (diff) | |
| download | qemu-kvm-66896cb803b4865c0c35b218dbc407e1fcf7f7f7.tar.gz qemu-kvm-66896cb803b4865c0c35b218dbc407e1fcf7f7f7.tar.bz2 qemu-kvm-66896cb803b4865c0c35b218dbc407e1fcf7f7f7.zip | |
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 3cef02115..7c3d4724d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5162,7 +5162,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) NEON_GET_REG(T0, rm, pass * 2); NEON_GET_REG(T1, rm, pass * 2 + 1); switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; case 2: /* no-op */ break; default: abort(); @@ -5173,7 +5173,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } else { gen_op_movl_T0_T1(); switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; default: abort(); } @@ -5315,7 +5315,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) switch (op) { case 1: /* VREV32 */ switch (size) { - case 0: tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]); break; + case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; case 1: gen_swap_half(cpu_T[0]); break; default: return 1; } @@ -6568,7 +6568,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 7)) gen_rev16(tmp); else - tcg_gen_bswap_i32(tmp, tmp); + tcg_gen_bswap32_i32(tmp, tmp); } store_reg(s, rd, tmp); } else { @@ -7384,7 +7384,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) gen_helper_rbit(tmp, tmp); break; case 0x08: /* rev */ - tcg_gen_bswap_i32(tmp, tmp); + tcg_gen_bswap32_i32(tmp, tmp); break; case 0x09: /* rev16 */ gen_rev16(tmp); @@ -8518,7 +8518,7 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s) rd = insn & 0x7; tmp = load_reg(s, rn); switch ((insn >> 6) & 3) { - case 0: tcg_gen_bswap_i32(tmp, tmp); break; + case 0: tcg_gen_bswap32_i32(tmp, tmp); break; case 1: gen_rev16(tmp); break; case 3: gen_revsh(tmp); break; default: goto illegal_op; |