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* target-arm/cpu.h: Make cpu_init("nonexistent cpu") return NULLPeter Maydell2012-05-101-1/+9
* target-arm: When setting FPSCR.QC, don't clear other FPSCR bitsMatt Craighead2012-05-101-1/+1
* target-arm: Make SETEND respect bswap_code (BE8) settingPeter Maydell2012-04-271-4/+4
* target-arm: Move A9 config_base_address reset value to ARMCPUPeter Maydell2012-04-272-3/+2
* target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber2012-04-274-7/+7
* target-arm: Move reset handling to arm_cpu_resetPeter Maydell2012-04-212-99/+92
* target-arm: Drop cpu_reset_model_id()Peter Maydell2012-04-211-58/+1
* target-arm: Move cache ID register setup to cpu specific init fnsPeter Maydell2012-04-213-11/+18
* target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_resetPeter Maydell2012-04-211-2/+1
* target-arm: Move feature register setup to per-CPU init fnsPeter Maydell2012-04-213-59/+122
* target-arm: Move iWMMXT wCID reset to cpu_state_resetPeter Maydell2012-04-211-1/+4
* target-arm: Drop JTAG_ID documentationPeter Maydell2012-04-211-2/+0
* target-arm: Move SCTLR reset value setup to per cpu init fnsPeter Maydell2012-04-213-12/+25
* target-arm: Move CTR setup to per cpu init fnsPeter Maydell2012-04-213-12/+24
* target-arm: Move MVFR* setup to per cpu init fnsPeter Maydell2012-04-213-12/+18
* target-arm: Move FPSID config to cpu init fnsPeter Maydell2012-04-213-8/+12
* target-arm: Move feature bit settings to CPU init fnsPeter Maydell2012-04-214-99/+137
* target-arm: Add QOM subclasses for each ARM cpu implementationPeter Maydell2012-04-213-65/+282
* target-arm: remind to keep arm features in sync with linux-user/elfload.cBenoit Canet2012-04-211-0/+4
* Use uintptr_t for various op related functionsBlue Swirl2012-04-141-5/+3
* Userspace ARM BE8 supportPaul Brook2012-04-063-10/+42
* ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers2012-03-303-1/+3
* target-arm: Minimalistic CPU QOM'ificationAndreas Färber2012-03-294-1/+139
* target-arm: Drop cpu_arm_close()Andreas Färber2012-03-292-6/+0
* target-arm: Decode SETEND correctly in ThumbPeter Maydell2012-03-151-23/+40
* target-arm: Clear IT bits when taking exceptions in v7MPeter Maydell2012-03-151-1/+2
* target-arm: Fix typo in ARM946 cp15 c5 handlingPeter Maydell2012-03-151-1/+1
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-1/+1
* target-arm: Don't overuse CPUStateAndreas Färber2012-03-146-195/+195
* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-141-2/+2
* target-arm: Clean includesStefan Weil2012-02-281-5/+0
* target-arm/helper.c: tb_flush() on CPU resetPeter Maydell2012-02-171-0/+5
* target-arm/helper.c: Correct FPSID value for Cortex-A9Peter Maydell2012-02-171-1/+1
* Add Cortex-A15 CPU definitionPeter Maydell2012-01-252-5/+52
* Add dummy implementation of generic timer cp15 registersPeter Maydell2012-01-252-2/+11
* arm: store the config_base_register during cpu_resetMark Langsdorf2012-01-251-0/+3
* target-arm/helper.c: Don't assume softfloat int32 is 32 bits onlyPeter Maydell2012-01-251-1/+1
* target-arm: Fix implementation of TLB invalidate operationsPeter Maydell2012-01-251-7/+6
* arm: Add dummy support for co-processor 15's secure config registerRob Herring2012-01-133-1/+13
* target-arm: Fix errors in decode of M profile CPSPeter Maydell2012-01-131-4/+4
* arm: add dummy A9-specific cp15 registersMark Langsdorf2012-01-053-1/+59
* target-arm: Ignore attempts to set invalid modes in CPSRPeter Maydell2012-01-051-1/+29
* target-arm: Don't use cpu_single_env in bank_number()Peter Maydell2012-01-051-6/+6
* target-arm: Infer VFPv3 feature from VFPv4Andreas Färber2011-12-131-1/+3
* target-arm: Infer VFP feature from VFPv3Andreas Färber2011-12-131-3/+3
* target-arm: Infer Thumb division feature from M profileAndreas Färber2011-12-131-1/+3
* target-arm: Infer Thumb2 feature from ARMv7Andreas Färber2011-12-131-4/+1
* target-arm: Infer AUXCR feature from ARMv6Andreas Färber2011-12-131-5/+3
* target-arm: Infer ARMv6(K) feature from ARMv7Andreas Färber2011-12-131-4/+5
* target-arm: Infer ARMv6 feature from v6KAndreas Färber2011-12-131-5/+3