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path: root/target-i386/helper.h
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* target-i386: implement lzcnt emulationAndre Przywara2009-10-231-0/+1
| | | | | | | | | | | | | lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-i386: add RDTSCP supportAndre Przywara2009-10-041-0/+1
| | | | | | | | | | | | | | RDTSCP reads the time stamp counter and atomically also the content of a 32-bit MSR, which can be freely set by the OS. This allows CPU local data to be queried by userspace. Linux uses this to allow a fast implementation of the getcpu() syscall, which uses the vsyscall page to avoid a context switch. AMD CPUs since K8RevF and Intel CPUs since Nehalem support this instruction. RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* x86: Add support for resume flagJan Kiszka2009-05-221-0/+1
| | | | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
* TCG variable type checking.pbrook2008-11-171-191/+188
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* SYSENTER/SYSEXIT IA-32e implementation (Alexander Graf).balrog2008-09-251-1/+1
| | | | | | | | | | | On Intel CPUs, sysenter and sysexit are valid in 64-bit mode. This patch makes both 64-bit aware and enables them for Intel CPUs. Add cpu save/load for 64-bit wide sysenter variables. Signed-off-by: Alexander Graf <agraf@suse.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5318 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
* HLT, MWAIT and MONITOR insn fixes (initial patch by Alexander Graf)bellard2008-06-181-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4746 c046a42c-6fe2-441c-8c8c-71466251a162
* reworked SVM interrupt handling logic - fixed vmrun EIP saved value - ↵bellard2008-06-041-4/+1
| | | | | | reworked cr8 handling - added CPUState.hflags2 git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4662 c046a42c-6fe2-441c-8c8c-71466251a162
* 32 bit SVM fixes - INVLPG and INVLPGA updatesbellard2008-06-041-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4660 c046a42c-6fe2-441c-8c8c-71466251a162
* SVM reworkbellard2008-05-281-1/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4605 c046a42c-6fe2-441c-8c8c-71466251a162
* proper helper definition registering (all targets must do that)bellard2008-05-221-189/+192
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4530 c046a42c-6fe2-441c-8c8c-71466251a162
* cmpxchg8b fix - added cmpxchg16bbellard2008-05-221-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4522 c046a42c-6fe2-441c-8c8c-71466251a162
* convert eflags manipulation insns to TCGbellard2008-05-211-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4515 c046a42c-6fe2-441c-8c8c-71466251a162
* converted LSL/LAR/VERW/VERR to TCG - force 16 bit memory access for LSL/LARbellard2008-05-211-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4513 c046a42c-6fe2-441c-8c8c-71466251a162
* converted INTO/CMPXCHG8B to TCGbellard2008-05-211-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4510 c046a42c-6fe2-441c-8c8c-71466251a162
* BSR/BSF TCG conversionbellard2008-05-171-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4477 c046a42c-6fe2-441c-8c8c-71466251a162
* converted condition code supprot to TCG - converted shift ops to TCGbellard2008-05-171-0/+11
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4470 c046a42c-6fe2-441c-8c8c-71466251a162
* converted more helpers to TCG - fixed some SVM issuesbellard2008-05-151-11/+39
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
* converted more helpers to TCGbellard2008-05-121-2/+73
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4447 c046a42c-6fe2-441c-8c8c-71466251a162
* converted x87 FPU ops to TCGbellard2008-05-121-0/+89
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4444 c046a42c-6fe2-441c-8c8c-71466251a162
* converted SSE/MMX ops to TCGbellard2008-05-121-0/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
* use the TCG code generatorbellard2008-02-011-0/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162