Get Gentoo!
gentoo.org sites
gentoo.org Wiki Bugs Forums Packages
Planet Archives Sources
Infra Status
aboutsummaryrefslogtreecommitdiff
path: root/opcodes/riscv-opc.c
Commit message (Expand)AuthorAgeFilesLines
* RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclip...Nelson Chu2024-11-221-0/+14
* RISC-V: Add Zcmt instructions and csr.Jiawei2024-11-201-0/+23
* RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2024-09-031-0/+222
* RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2024-08-271-0/+9
* RISC-V: map zext.h to pack/packw if Zbkb is enabledHau Hsu2024-08-061-2/+2
* RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2024-08-061-0/+19
* RISC-V: Add support for Zcmop extensionXiao Zeng2024-08-061-0/+10
* RISC-V: Add support for Zimop extensionXiao Zeng2024-08-061-0/+42
* RISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich2024-07-051-102/+102
* RISC-V: Add Zabha extension CAS instructions.Jiawei2024-06-281-0/+8
* RISC-V: Add SiFive cease extension v1.0Hau Hsu2024-06-181-0/+3
* RISC-V: Support Zacas extension.Gianluca Guida2024-06-181-0/+26
* RISC-V: Add support for Zvfbfwma extensionXiao Zeng2024-06-061-0/+4
* RISC-V: Add support for Zvfbfmin extensionXiao Zeng2024-06-061-0/+4
* RISC-V: Add support for Zfbfmin extensionXiao Zeng2024-06-061-0/+5
* RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett2024-06-051-0/+26
* RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett2024-06-051-0/+4
* RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett2024-06-051-0/+3
* RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu2024-05-081-88/+88
* RISC-V: Support Zcmp push/pop instructions.Jiawei2024-04-091-0/+20
* RISC-V: Support Zabha extension.Jiawei2024-03-081-0/+74
* RISC-V: Add assembly support for TLSDESC.Tatsuyuki Ishi2024-02-291-0/+1
* RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma2024-01-051-1/+13
* Update year range in copyright notice of binutils filesAlan Modra2024-01-041-1/+1
* RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma2023-12-291-0/+5
* RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma2023-12-141-1/+1
* RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2023-12-011-0/+30
* RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner2023-12-011-10/+10
* RISC-V: drop leftover match_never() referencesJan Beulich2023-11-241-4/+4
* RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich2023-11-241-2/+2
* RISC-V: disallow x0 with certain macro-insnsJan Beulich2023-11-241-45/+45
* RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+15
* RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+19
* RISC-V: Add reductions instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+16
* RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...Jin Ma2023-11-231-0/+86
* RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma2023-11-231-0/+36
* RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+143
* RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+18
* RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+280
* RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma2023-11-231-0/+44
* RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...Jin Ma2023-11-231-0/+4
* RISC-V: Add support for XCValu extension in CV32E40PMary Bennett2023-11-071-0/+35
* RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett2023-11-071-0/+26
* RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich2023-11-031-19/+19
* RISC-V: Clarify the naming rules of vendor operands.Nelson Chu2023-09-071-65/+65
* RISC-V: fold duplicate code in vector_macro()Jan Beulich2023-09-051-2/+2
* RISC-V: move various alias entriesJan Beulich2023-09-011-35/+35
* RISC-V: Make XVentanaCondOps RV64 onlyTsukasa OI2023-08-301-2/+2
* RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI2023-08-151-1/+1
* RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI2023-08-151-0/+12