Bump to 3.4.6, and mark 3.4.5 as stable.

Package-Manager: portage-2.1_rc3

8 files changed, 574 insertions, 9 deletions

diff --git a/sys-devel/gcc-mips64/ChangeLog b/sys-devel/gcc-mips64/ChangeLog
index 006a4b2e3205..62267e14e585 100644
--- a/sys-devel/gcc-mips64/ChangeLog
+++ b/sys-devel/gcc-mips64/ChangeLog
@@ -1,6 +1,13 @@
 # ChangeLog for sys-devel/gcc-mips64
-# Copyright 2000-2005 Gentoo Foundation; Distributed under the GPL v2
-# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/ChangeLog,v 1.17 2005/12/28 18:46:16 kumba Exp $
+# Copyright 2000-2006 Gentoo Foundation; Distributed under the GPL v2
+# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/ChangeLog,v 1.18 2006/05/30 00:20:01 kumba Exp $
+
+*gcc-mips64-3.4.6 (30 May 2006)
+
+  30 May 2006; Joshua Kinard <kumba@gentoo.org>
+  +files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch,
+  gcc-mips64-3.4.5.ebuild, +gcc-mips64-3.4.6.ebuild:
+  Bump to 3.4.6, and mark 3.4.5 as stable.
 
   28 Dec 2005; Joshua Kinard <kumba@gentoo.org> gcc-mips64-3.4.4.ebuild,
   gcc-mips64-3.4.5.ebuild:
diff --git a/sys-devel/gcc-mips64/Manifest b/sys-devel/gcc-mips64/Manifest
index a2b70b260afb..91beedc5fbaa 100644
--- a/sys-devel/gcc-mips64/Manifest
+++ b/sys-devel/gcc-mips64/Manifest
@@ -1,10 +1,52 @@
-MD5 7c03c09f3203111de39c2642e2f98799 ChangeLog 3715
-MD5 4b8b4306f268900392bbd0319bdfdf65 files/digest-gcc-mips64-3.4.4 64
-MD5 ba0f5e25062066184f3513100252770f files/digest-gcc-mips64-3.4.5 64
+AUX gcc-3.3.4-gentoo-branding.patch 874 RMD160 6fb3fb88248b9ee25f7eb1f5fea6303b723afbc6 SHA1 a0e1d7f867fa281fff061bf055c0b6d4dcef2ba1 SHA256 aa4c37bf45c1b67ac0f24fed850dca130933351f9ed35672599b6fcb96cfd0a3
 MD5 e411938ca2908079a2359fed5cb3b442 files/gcc-3.3.4-gentoo-branding.patch 874
+RMD160 6fb3fb88248b9ee25f7eb1f5fea6303b723afbc6 files/gcc-3.3.4-gentoo-branding.patch 874
+SHA256 aa4c37bf45c1b67ac0f24fed850dca130933351f9ed35672599b6fcb96cfd0a3 files/gcc-3.3.4-gentoo-branding.patch 874
+AUX gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118 RMD160 4fdcab01f80301f39b7c088750f180d95f03384e SHA1 d5c090642444b300980301526245140717893e8d SHA256 65261236a04002d6db44d4522f1dd0ebc34dc8f17244feed535230900c235fe5
 MD5 1134e9dabbd6dfba1d91015851f02a2b files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
+RMD160 4fdcab01f80301f39b7c088750f180d95f03384e files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
+SHA256 65261236a04002d6db44d4522f1dd0ebc34dc8f17244feed535230900c235fe5 files/gcc-3.4.2-mips-ip28_cache_barriers-v2.patch 14118
+AUX gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951 RMD160 fa7caaf9b41ed22ed5ccb1649c693248895ec3fb SHA1 cc60d62597865fef56844bc3e92640f2c64a98db SHA256 8cef3779bc962b9a9c20daabea28791514b6f54824659e2f5824c493cdc3f6c7
+MD5 d49acaf7a8dc1f939f4d05cee97ac3a5 files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
+RMD160 fa7caaf9b41ed22ed5ccb1649c693248895ec3fb files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
+SHA256 8cef3779bc962b9a9c20daabea28791514b6f54824659e2f5824c493cdc3f6c7 files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch 12951
+AUX gcc-3.4.2-mips-ip28_cache_barriers.patch 12545 RMD160 fe86ed49435828cdcfe0692aa4a8816d684268af SHA1 a87d993d01416a399e30f5143c1e5455979e8b67 SHA256 e88a5539732816deccaa195f48ee1fd719de82a91866cfe3ec0ca9474daafb4e
 MD5 f3a1b668077c6486c542dcef1cdd9672 files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
+RMD160 fe86ed49435828cdcfe0692aa4a8816d684268af files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
+SHA256 e88a5539732816deccaa195f48ee1fd719de82a91866cfe3ec0ca9474daafb4e files/gcc-3.4.2-mips-ip28_cache_barriers.patch 12545
+AUX gcc-3.4.x-mips-add-march-r10k.patch 14248 RMD160 25f72003b241836ec3e08ae4108a39b0ffd9b170 SHA1 abc47bce08334eafc65d167cfdbaaa0c68663248 SHA256 10d6947954f03145d8ac16f497826cf25583d37f0e1e63b9df1a33d91f59e2c8
 MD5 b2922cfe76692e7d2b373a0a255f405e files/gcc-3.4.x-mips-add-march-r10k.patch 14248
+RMD160 25f72003b241836ec3e08ae4108a39b0ffd9b170 files/gcc-3.4.x-mips-add-march-r10k.patch 14248
+SHA256 10d6947954f03145d8ac16f497826cf25583d37f0e1e63b9df1a33d91f59e2c8 files/gcc-3.4.x-mips-add-march-r10k.patch 14248
+DIST gcc-3.4.4.tar.bz2 27565872 RMD160 cb9c4154c9e34d45c80eb80fd7bc30b036e6fec4 SHA1 dbe5935c04f799c77b49d6806f9d7db6d9b5cd35 SHA256 3444179840638cb8664e8e53604900c4521d29d57785a5091202ee4937d8d0fd
+DIST gcc-3.4.5.tar.bz2 28254232 RMD160 611ad033a76ada49d43529fc694142e856a039fa SHA1 389bcc98e391545e501c05557a8651104beac059 SHA256 be5738a94076052453894dd7d35b1efbb017bba1da0b28495d145f98fe018a09
+DIST gcc-3.4.6.tar.bz2 28193401 RMD160 b15003368cedc7964f6ceaee0c39ddc43a46c442 SHA1 97b290fdc572c8e490b3b39f243e69bacad23c2b SHA256 7791a601878b765669022b8b3409fba33cc72f9e39340fec8af6d0e6f72dec39
+EBUILD gcc-mips64-3.4.4.ebuild 3861 RMD160 81bbb849727ab49b2aab2de6e0099def1b6c6ec8 SHA1 982f3bb408a8bff80890e80f0c24ac1a073a8e30 SHA256 722650f608951606ee804d8114b0a263581fb23f8261c5a9da542ffd45777d3b
 MD5 f27962dff9b3cd0fb879336ce36d13d4 gcc-mips64-3.4.4.ebuild 3861
-MD5 fcd140a56d47a50a249bad3ba55f448d gcc-mips64-3.4.5.ebuild 3850
+RMD160 81bbb849727ab49b2aab2de6e0099def1b6c6ec8 gcc-mips64-3.4.4.ebuild 3861
+SHA256 722650f608951606ee804d8114b0a263581fb23f8261c5a9da542ffd45777d3b gcc-mips64-3.4.4.ebuild 3861
+EBUILD gcc-mips64-3.4.5.ebuild 3849 RMD160 dc08b3cdecb2495ec4eeb6c142e3bcde34531cf0 SHA1 3378e07173fced7adf850c5218e62798d4d15624 SHA256 a8b7707b7db92f3218b1b98d7fbe0abfd33f10ce82934930a0fa0b9e710b1782
+MD5 d5008212a0ce03ae155e2dbd7037dce2 gcc-mips64-3.4.5.ebuild 3849
+RMD160 dc08b3cdecb2495ec4eeb6c142e3bcde34531cf0 gcc-mips64-3.4.5.ebuild 3849
+SHA256 a8b7707b7db92f3218b1b98d7fbe0abfd33f10ce82934930a0fa0b9e710b1782 gcc-mips64-3.4.5.ebuild 3849
+EBUILD gcc-mips64-3.4.6.ebuild 3850 RMD160 7ef6c01a0d3cc77bebe20a68f25ba8bfe30ab0c7 SHA1 9e78a4e31cb6c568b8344a8ff5086df7ae9f127e SHA256 0a40e2bfe7c2e696ff5849a8c494469b976c6044c01de172e4a562ae04c00d05
+MD5 e52e1f369179c9d6aadd2704df7a5a53 gcc-mips64-3.4.6.ebuild 3850
+RMD160 7ef6c01a0d3cc77bebe20a68f25ba8bfe30ab0c7 gcc-mips64-3.4.6.ebuild 3850
+SHA256 0a40e2bfe7c2e696ff5849a8c494469b976c6044c01de172e4a562ae04c00d05 gcc-mips64-3.4.6.ebuild 3850
+MISC ChangeLog 3947 RMD160 414634feb4b35e89a0dce6bfe9ca3785dbdc1741 SHA1 2b7d115761abd20a18ea8bb8b601b1f2ed534857 SHA256 74cf21fd2200701be5cff4d1052048aeb4a636bc75bdfb858bae63fe507abf54
+MD5 de9ace16207e9736fdccb9966465f711 ChangeLog 3947
+RMD160 414634feb4b35e89a0dce6bfe9ca3785dbdc1741 ChangeLog 3947
+SHA256 74cf21fd2200701be5cff4d1052048aeb4a636bc75bdfb858bae63fe507abf54 ChangeLog 3947
+MISC metadata.xml 364 RMD160 dcd8036943975744729bdacd32830685312e2859 SHA1 d6dfbbe9a53e6b572cee01e3b916e156bb8c06e4 SHA256 389476a4f82ae4c3279e1c36e7db17a470c54b84507a942ee5b99096e7083d04
 MD5 efda60760635b5f29e31a8f730a73086 metadata.xml 364
+RMD160 dcd8036943975744729bdacd32830685312e2859 metadata.xml 364
+SHA256 389476a4f82ae4c3279e1c36e7db17a470c54b84507a942ee5b99096e7083d04 metadata.xml 364
+MD5 ea4c9ea57efd788dfe61ceca73bf8121 files/digest-gcc-mips64-3.4.4 238
+RMD160 39991729ee810f2a91b3d9845cd1a41ac719efc7 files/digest-gcc-mips64-3.4.4 238
+SHA256 dde905c841f735fdf555e215cb7e6988a650a1283cd898af44990c171db6e589 files/digest-gcc-mips64-3.4.4 238
+MD5 30fce0b5ce7788c37140089824712999 files/digest-gcc-mips64-3.4.5 238
+RMD160 cec68ae1f10278e63f35e3dc809e5383b19b1a7b files/digest-gcc-mips64-3.4.5 238
+SHA256 083f56ea3bbdb792eca0997ccfa044b2ba0e5a1c2d20aaaf7b0630dc430b71ec files/digest-gcc-mips64-3.4.5 238
+MD5 8fc27b2f831bbe81d5f3bc7005a44ca0 files/digest-gcc-mips64-3.4.6 238
+RMD160 e740aa34a8ebbb3a6b339afb74c9b7ad4dab824f files/digest-gcc-mips64-3.4.6 238
+SHA256 977bbf6314223f25cab3dcdb74a586dbadf8f3aa6218d570483f8b684a27e764 files/digest-gcc-mips64-3.4.6 238
diff --git a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.4 b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.4
index 222982e0095a..f79f3a048eb5 100644
--- a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.4
+++ b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.4
@@ -1 +1,3 @@
 MD5 b594ff4ea4fbef4ba9220887de713dfe gcc-3.4.4.tar.bz2 27565872
+RMD160 cb9c4154c9e34d45c80eb80fd7bc30b036e6fec4 gcc-3.4.4.tar.bz2 27565872
+SHA256 3444179840638cb8664e8e53604900c4521d29d57785a5091202ee4937d8d0fd gcc-3.4.4.tar.bz2 27565872
diff --git a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.5 b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.5
index ded991406cd1..c527d0c6a70b 100644
--- a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.5
+++ b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.5
@@ -1 +1,3 @@
 MD5 7c3c3c3e764dcee5eb771432062d69e1 gcc-3.4.5.tar.bz2 28254232
+RMD160 611ad033a76ada49d43529fc694142e856a039fa gcc-3.4.5.tar.bz2 28254232
+SHA256 be5738a94076052453894dd7d35b1efbb017bba1da0b28495d145f98fe018a09 gcc-3.4.5.tar.bz2 28254232
diff --git a/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6 b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6
new file mode 100644
index 000000000000..b439e21c4406
--- /dev/null
+++ b/sys-devel/gcc-mips64/files/digest-gcc-mips64-3.4.6
@@ -0,0 +1,3 @@
+MD5 4a21ac777d4b5617283ce488b808da7b gcc-3.4.6.tar.bz2 28193401
+RMD160 b15003368cedc7964f6ceaee0c39ddc43a46c442 gcc-3.4.6.tar.bz2 28193401
+SHA256 7791a601878b765669022b8b3409fba33cc72f9e39340fec8af6d0e6f72dec39 gcc-3.4.6.tar.bz2 28193401
diff --git a/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch b/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
new file mode 100644
index 000000000000..02edc3709e2a
--- /dev/null
+++ b/sys-devel/gcc-mips64/files/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
@@ -0,0 +1,366 @@
+diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.c gcc-3.4.6/gcc/config/mips/mips.c
+--- gcc-3.4.6.orig/gcc/config/mips/mips.c	2005-07-31 04:35:15.000000000 -0400
++++ gcc-3.4.6/gcc/config/mips/mips.c	2006-04-08 17:41:44.000000000 -0400
+@@ -8801,6 +8801,11 @@ mips_reorg (void)
+ 	dbr_schedule (get_insns (), rtl_dump_file);
+       mips_avoid_hazards ();
+     }
++  if (mips_r10k_cache_barrier)
++    {
++      static int r10k_insert_cache_barriers (void);
++      r10k_insert_cache_barriers ();
++    }
+ }
+ 
+ /* We need to use a special set of functions to handle hard floating
+@@ -9661,5 +9666,5 @@ irix_section_type_flags (tree decl, cons
+ }
+ 
+ #endif /* TARGET_IRIX */
+-
++#include "r10k-cacheb.c"
+ #include "gt-mips.h"
+diff -Naurp gcc-3.4.6.orig/gcc/config/mips/mips.h gcc-3.4.6/gcc/config/mips/mips.h
+--- gcc-3.4.6.orig/gcc/config/mips/mips.h	2004-07-14 20:42:49.000000000 -0400
++++ gcc-3.4.6/gcc/config/mips/mips.h	2006-04-08 17:41:01.000000000 -0400
+@@ -122,6 +122,7 @@ extern const char *mips_tune_string;    
+ extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
+ extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
+ extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
++extern const char *mips_r10k_cache_barrier;/* for -mr10k-cache-barrier[={1,2}] */
+ extern int mips_string_length;		/* length of strings for mips16 */
+ extern const struct mips_cpu_info mips_cpu_info_table[];
+ extern const struct mips_cpu_info *mips_arch_info;
+@@ -752,6 +753,10 @@ extern const struct mips_cpu_info *mips_
+       N_("Don't call any cache flush functions"), 0},			\
+   { "flush-func=", &mips_cache_flush_func,				\
+       N_("Specify cache flush function"), 0},				\
++  { "r10k-cache-barrier", &mips_r10k_cache_barrier,			\
++      N_("[=1|2]\tGenerate cache barriers for SGI Indigo2/O2 R10k"), 0},	\
++  { "ip28-cache-barrier", &mips_r10k_cache_barrier,			\
++      N_(""), 0},	\
+ }
+ 
+ /* This is meant to be redefined in the host dependent files.  */
+diff -Naurp gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c gcc-3.4.6/gcc/config/mips/r10k-cacheb.c
+--- gcc-3.4.6.orig/gcc/config/mips/r10k-cacheb.c	1969-12-31 19:00:00.000000000 -0500
++++ gcc-3.4.6/gcc/config/mips/r10k-cacheb.c	2006-04-08 17:41:22.000000000 -0400
+@@ -0,0 +1,318 @@
++/* Subroutines used for MIPS code generation: generate cache-barriers
++   for SiliconGraphics IP28 and IP32/R10000 kernel-code.
++   Copyright (C) 2005,2006 peter fuerst, pf@net.alphadv.de.
++
++This file is intended to become part of GCC.
++
++This file is free software; you can redistribute it and/or modify it
++under the terms of the GNU General Public License as published
++by the Free Software Foundation; either version 2, or (at your
++option) any later version.
++
++This file is distributed in the hope that it will be useful,
++but WITHOUT ANY WARRANTY; without even the implied warranty of
++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++GNU General Public License for more details.
++
++You should have received a copy of the GNU General Public License
++along with GCC; see the file COPYING.  If not, write to the
++Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
++MA  02110-1301  USA.  */
++
++
++#define ASM_R10K_CACHE_BARRIER	"cache 0x14,0($sp)"
++
++/* Some macros, ported back from 4.x ... */
++
++#define CALL_P(X)  (GET_CODE (X) == CALL_INSN)
++#define MEM_P(X)   (GET_CODE (X) == MEM)
++#define NONJUMP_INSN_P(X)  (GET_CODE (X) == INSN)
++
++#define SEQ_BEGIN(insn)                        \
++  (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE  \
++   ? XVECEXP (PATTERN (insn), 0, 0)                        \
++   : (insn))
++
++#define SEQ_END(insn)                          \
++  (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE      \
++   ? XVECEXP (PATTERN (insn), 0, XVECLEN (PATTERN (insn), 0) - 1)  \
++   : (insn))
++
++#define FOR_EACH_SUBINSN(subinsn, insn)        \
++  for ((subinsn) = SEQ_BEGIN (insn);       \
++       (subinsn) != NEXT_INSN (SEQ_END (insn));    \
++       (subinsn) = NEXT_INSN (subinsn))
++
++
++/* Nonzero means generate special cache barriers to inhibit speculative
++   stores which might endanger cache coherency or reference invalid
++   addresses (especially on SGI's Indigo2 R10k (IP28)).  */
++const char *mips_r10k_cache_barrier;
++static int TARGET_R10K_SPECEX;
++
++/* Check, whether an instruction is a possibly harmful store instruction,
++   i.e. a store which might cause damage, if speculatively executed. */
++
++/* Return truth value whether the expression `*memx' instantiates
++   (mem:M (not (stackpointer_address or constant))). */
++
++static int
++is_stack_pointer (rtx *x, void *data)
++{
++  return (*x == stack_pointer_rtx);
++}
++
++static int
++check_p_mem_expr (rtx *memx, void *data)
++{
++  if (!MEM_P (*memx) || for_each_rtx (memx, is_stack_pointer, 0))
++    return 0;
++
++  /* Stores/Loads to/from constant addresses can be considered
++     harmless, since:
++     1)  the address is always valid, even when taken speculatively.
++     2a) the location is (hopefully) never used as a dma-target, thus
++         there is no danger of cache-inconsistency.
++     2b) uncached loads/stores are guaranteed to be non-speculative. */
++  if ( CONSTANT_P(XEXP (*memx, 0)) )
++    return 0;
++
++  return 1;
++}
++
++/* Return truth value whether we find (set (mem:M (non_stackpointer_address)
++   ...)) in instruction-pattern `body'.
++   Here we assume, that addressing with the stackpointer accesses neither
++   uncached-aliased nor invalid memory.
++   (May be, this applies to the global pointer and frame pointer also,
++   but its saver not to assume it. And probably it's not worthwile to
++   regard these registers)
++
++   Speculative loads from invalid addresses also cause bus errors...
++   So check for (set (reg:M ...) (mem:M (non_stackpointer_address)))
++   too, unless there is an enhanced bus-error handler. */
++
++static int
++check_p_pattern_for_store (rtx *body, void *data)
++{
++  if (*body && GET_CODE (*body) == SET)
++    {
++      /* Cache-barriers for SET_SRC may be requested as well. */
++      if (!(TARGET_R10K_SPECEX & 2))
++        body = &SET_DEST(*body);
++
++      if (for_each_rtx (body, check_p_mem_expr, 0))
++        return 1;
++
++      /* Don't traverse sub-expressions again. */
++      return -1;
++    }
++  return 0;
++}
++
++static int
++strmatch (const char *txt, const char *match)
++{
++  return !strncmp(txt, match, strlen (match));
++}
++
++/* Check for (ins (set (mem:M (dangerous_address)) ...)) or end of the
++   current basic block in instruction `insn'.
++   `state': (internal) recursion-counter and delayslot-flag
++   Criteria to recognize end-of/next basic-block are reduplicated here
++   from final_scan_insn.
++   return >0: `insn' is critical.
++   return <0: `insn' is at end of current basic-block.
++   return 0:  `insn' can be ignored. */
++
++static int
++check_insn_for_store (int state, rtx insn)
++{
++  rtx body;
++
++  if (INSN_DELETED_P (insn))
++    return 0;
++
++  if (LABEL_P (insn))
++    return -1;
++
++  if (CALL_P (insn) || JUMP_P (insn) || NONJUMP_INSN_P (insn))
++    {
++      body = PATTERN (insn);
++      if (GET_CODE (body) == SEQUENCE)
++        {
++          /* A delayed-branch sequence. */
++          rtx insq;
++          FOR_EACH_SUBINSN(insq, insn)
++            if (! INSN_DELETED_P (insq))
++              {
++                /* |1: delay-slot completely contained in sequence. */
++                if (check_insn_for_store (8+state|1, insq) > 0)
++                  return 1;
++              }
++          /* Following a (conditional) branch sequence, we have a new
++             basic block.  */
++          if (JUMP_P (SEQ_BEGIN(insn)))
++            return -1;
++          /* Handle a call sequence like a conditional branch sequence. */
++          if (CALL_P (SEQ_BEGIN(insn)))
++            return -1;
++        }
++      if (GET_CODE (body) == PARALLEL)
++        if (for_each_rtx (&body, check_p_pattern_for_store, 0))
++           return 1;
++
++      /* Now, only a `simple' INSN or JUMP_INSN remains to be checked. */
++      if (NONJUMP_INSN_P (insn))
++        {
++          /* Since we don't know what's inside, we must take inline
++             assembly to be dangerous. */
++          if (GET_CODE (body) == ASM_INPUT)
++            {
++              const char *t = XSTR (body, 0);
++              if (t && !strmatch(t, ASM_R10K_CACHE_BARRIER))
++                return 1;
++            }
++
++          if (check_p_pattern_for_store (&body, 0) > 0)
++            return 1;
++        }
++      /* Handle a CALL_INSN instruction like a conditional branch. */
++      if (JUMP_P (insn) || CALL_P (insn))
++        {
++          /* Following a (conditional) branch, we have a new basic block. */
++          /* But check insn(s) in delay-slot first.  If we could know in
++             advance that this jump is in `.reorder' mode, where gas will
++             insert a `nop' into the delay-slot, we could skip this test.
++             Since we don't know, always assume `.noreorder', sometimes
++             emitting a cache-barrier, that isn't needed.  */
++          /* But if we are here recursively, already checking a (pseudo-)
++             delay-slot, we are done.  */
++          if ( !(state & 1) )
++            for (insn = NEXT_INSN (insn); insn; insn = NEXT_INSN (insn))
++              {
++                if (LABEL_P (insn) || CALL_P (insn) || JUMP_P (insn))
++                  /* Not in delay-slot at all. */
++                  break;
++
++                if (NONJUMP_INSN_P (insn))
++                  {
++                    if (GET_CODE (PATTERN (insn)) == SEQUENCE)
++                      /* Not in delay-slot at all. */
++                      break;
++
++                    if (check_insn_for_store (8+state|1, insn) > 0)
++                      return 1;
++                    /* We're done anyway. */
++                    break;
++                  }
++                /* skip NOTE,... */;
++              }
++          return -1;
++        }
++    }
++  return 0;
++}
++
++
++/* Scan a basic block, starting with `insn', for a possibly harmful store
++   instruction.  If found, output a cache barrier at the start of this
++   block.  */
++
++static int
++bb_insert_store_cache_barrier (rtx head, rtx nxtb)
++{
++  rtx insn = head;
++
++  if (!insn || insn == nxtb)
++     return 0;
++
++  while ((insn = NEXT_INSN (insn)) && insn != nxtb)
++    {
++      int found;
++
++      if (NOTE_INSN_BASIC_BLOCK_P(insn)) /* See scan_1_bb_for_store() */
++        break;
++      
++      found = check_insn_for_store (0, insn);
++      if (found < 0)
++        break;
++      if (found > 0)
++        {
++          /* found critical store instruction */
++          insn = gen_rtx_ASM_INPUT (VOIDmode,
++                                    ASM_R10K_CACHE_BARRIER "\t"
++                                    ASM_COMMENT_START " Cache Barrier");
++          /* Here we rely on the assumption, that an explicit delay-slot
++             - if any - is already embedded (in a sequence) in 'head'! */
++          insn = emit_insn_after (insn, head);
++          return 1;
++        }
++    }
++  return 0;
++}
++
++
++/* Scan one basic block for a possibly harmful store instruction.
++   If found, insert a cache barrier at the start of this block,
++   return number of inserted cache_barriers. */
++
++static int
++scan_1_bb_for_store (rtx head, rtx end)
++{
++  rtx nxtb;
++  int count;
++
++  /* Note: 'end' is not necessarily reached from 'head' (hidden in
++     SEQUENCE, PARALLEL), but 'nxtb' is. */
++  nxtb = NEXT_INSN (end);
++
++  /* Each basic block starts with zero or more CODE_LABEL(s), followed
++     by one NOTE_INSN_BASIC_BLOCK.
++     Note: bb_head may equal next_insn(bb_end) already ! */
++  while (head && head != nxtb && LABEL_P (head))
++    head = NEXT_INSN (head);
++
++  if (!head || head == nxtb)
++    return 0;
++
++  /* Handle the basic block itself, at most up to next CALL_INSN. */
++  count = bb_insert_store_cache_barrier (head, nxtb);
++
++  /* 1) Handle any CALL_INSN instruction like a conditional branch.
++     2) There may be "basic blocks" in the list, which are no basic blocks
++        at all. (containing CODE_LABELs in the body or gathering several
++        other basic blocks (e.g. bb5 containing bb6,bb7,bb8)). */
++
++  while ((head = NEXT_INSN (head)) && head != nxtb)
++    {
++      if (INSN_DELETED_P (head))
++        continue;
++
++      /* Later we'll be called again for this bb on its own. */
++      if (NOTE_INSN_BASIC_BLOCK_P(head))
++        break;
++
++      if (CALL_P (SEQ_BEGIN (head)) || LABEL_P (head))
++        count += bb_insert_store_cache_barrier (head, nxtb);
++    }
++  return count;
++}
++
++static int
++r10k_insert_cache_barriers (void)
++{
++  if (mips_r10k_cache_barrier)
++    {
++      basic_block bb;
++
++      const char *s = mips_r10k_cache_barrier;
++      /* Default is to protect stores (only). */
++      TARGET_R10K_SPECEX = 1 | strtol(*s != '=' ? s:s+1, (char**)0, 0);
++
++      FOR_EACH_BB (bb)
++        if (0 <= bb->index)
++          scan_1_bb_for_store (BB_HEAD (bb), BB_END (bb));
++    }
++  return 0;
++}
diff --git a/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild b/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild
index 9f0e8cae08f2..a33ac3273f47 100644
--- a/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild
+++ b/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild
@@ -1,6 +1,6 @@
-# Copyright 1999-2005 Gentoo Foundation
+# Copyright 1999-2006 Gentoo Foundation
 # Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild,v 1.3 2005/12/28 18:46:16 kumba Exp $
+# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/gcc-mips64-3.4.5.ebuild,v 1.4 2006/05/30 00:20:01 kumba Exp $
 
 inherit eutils flag-o-matic
 
@@ -21,7 +21,7 @@ LICENSE="GPL-2 LGPL-2.1"
 SLOT="0"
 IUSE=""
 
-KEYWORDS="~mips"
+KEYWORDS="mips"
 
 DEPEND="virtual/libc
 	>=sys-devel/binutils-2.16.1
diff --git a/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild b/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild
new file mode 100644
index 000000000000..609cd7df2230
--- /dev/null
+++ b/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild
@@ -0,0 +1,143 @@
+# Copyright 1999-2006 Gentoo Foundation
+# Distributed under the terms of the GNU General Public License v2
+# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc-mips64/gcc-mips64-3.4.6.ebuild,v 1.1 2006/05/30 00:20:01 kumba Exp $
+
+inherit eutils flag-o-matic
+
+# Variables 
+MYARCH="$(echo ${PN} | cut -d- -f2)"
+TMP_P="${P/-${MYARCH}/}"
+TMP_PN="${PN/-${MYARCH}/}"
+I="/usr"
+BRANCH_UPDATE=""
+
+DESCRIPTION="Mips64 Kernel Compiler"
+HOMEPAGE="http://www.gnu.org/software/gcc/gcc.html"
+
+SRC_URI="ftp://gcc.gnu.org/pub/gcc/releases/${TMP_P}/${TMP_P}.tar.bz2"
+#	mirror://gentoo/${TMP_P}-branch-update-${BRANCH_UPDATE}.patch.bz2"
+
+LICENSE="GPL-2 LGPL-2.1"
+SLOT="0"
+IUSE=""
+
+KEYWORDS="~mips"
+
+DEPEND="virtual/libc
+	>=sys-devel/binutils-2.16.1
+	>=sys-devel/gcc-config-1.3.12-r4"
+
+RDEPEND="virtual/libc
+	>=sys-devel/gcc-config-1.3.12-r4
+	>=sys-libs/zlib-1.1.4
+	>=sys-apps/texinfo-4.2-r4
+	!build? ( >=sys-libs/ncurses-5.2-r2 )"
+
+# Ripped from toolchain.eclass
+gcc_version_patch() {
+	[ -z "$1" ] && die "no arguments to gcc_version_patch"
+
+	sed -i -e 's~\(const char version_string\[\] = ".....\).*\(".*\)~\1 @GENTOO@\2~' ${S}/gcc/version.c || die "failed to add @GENTOO@"
+	sed -i -e "s:@GENTOO@:$1:g" ${S}/gcc/version.c || die "failed to patch version"
+	sed -i -e 's~http:\/\/gcc\.gnu\.org\/bugs\.html~http:\/\/bugs\.gentoo\.org\/~' ${S}/gcc/version.c || die "failed to update bugzilla URL"
+}
+
+pkg_setup() {
+	# glibc or uclibc?
+	if use elibc_glibc; then
+		MYUSERLAND="gnu"
+	elif use elibc_uclibc; then
+		MYUSERLAND="uclibc"
+	fi
+}
+
+src_unpack() {
+	unpack ${A}
+	cd ${WORKDIR}
+	ln -s ${TMP_P} ${P}
+	cd ${S}
+
+	# Patch in Branch update
+	if [ ! -z "${BRANCH_UPDATE}" ]; then
+		epatch ${WORKDIR}/${TMP_P}-branch-update-${BRANCH_UPDATE}.patch
+	fi
+
+	# Adds -march=r10000 support to gcc
+	epatch ${FILESDIR}/gcc-3.4.x-mips-add-march-r10k.patch
+
+	# Allows building of kernels for IP28 systems (enable w/ -mip28-cache-barrier)
+	epatch ${FILESDIR}/gcc-3.4.2-mips-ip28_cache_barriers-v4.patch
+
+	# Make gcc's version info specific to Gentoo
+	gcc_version_patch "(Gentoo Linux ${PVR})"
+}
+
+src_compile() {
+	cd ${WORKDIR}
+	ln -s ${TMP_P} ${P}
+
+	append-flags "-Dinhibit_libc"
+
+	# Build in a separate build tree
+	mkdir -p ${WORKDIR}/build
+	cd ${WORKDIR}/build
+
+	einfo "Configuring GCC..."
+	if [ "`uname -m | grep 64`" ]; then
+		myconf="${myconf} --host=${MYARCH/64/}-unknown-linux-${MYUSERLAND}"
+	fi
+
+	addwrite "/dev/zero"
+	${S}/configure --prefix=${I} \
+		--disable-shared \
+		--disable-multilib \
+		--target=${MYARCH}-unknown-linux-${MYUSERLAND} \
+		--enable-languages=c \
+		--enable-threads=single \
+		${myconf} || die
+
+	einfo "Building GCC..."
+	S="${WORKDIR}/build" \
+	emake CFLAGS="${CFLAGS}" || die
+}
+
+src_install() {
+	# Do allow symlinks in ${I}/lib/gcc-lib/${CHOST}/${PV}/include as
+	# this can break the build.
+	for x in cd ${WORKDIR}/build/gcc/include/*
+	do
+		if [ -L ${x} ]
+		then
+			rm -f ${x}
+		fi
+	done
+
+	einfo "Installing GCC..."
+	# Do the 'make install' from the build directory
+	cd ${WORKDIR}/build
+	S="${WORKDIR}/build" \
+	make prefix=${D}${I} \
+		FAKE_ROOT="${D}" \
+		install || die
+
+	cd ${D}${I}/bin
+	ln -s ${MYARCH}-unknown-linux-${MYUSERLAND}-gcc gcc64
+	ln -s ${MYARCH}-unknown-linux-${MYUSERLAND}-gcc ${MYARCH}-linux-gcc
+}
+
+pkg_postinst() {
+	einfo ""
+	einfo "To facilitate an easier kernel build, you may wish to add the following line to your profile:"
+	einfo ""
+	einfo "For 2.4.x kernel builds:"
+	einfo "alias ${MYARCH}make=\"make ARCH=${MYARCH} CROSS_COMPILE=${MYARCH}-unknown-linux-${MYUSERLAND}-\""
+	einfo ""
+	einfo "For 2.6.x kernel builds:"
+	einfo "alias ${MYARCH}make=\"make ARCH=${MYARCH/64/} CROSS_COMPILE=${MYARCH}-unknown-linux-${MYUSERLAND}-\""
+	einfo ""
+	einfo "Then to compile a kernel, simply goto the kernel source directory, and issue:"
+	einfo "${MYARCH}make <target>"
+	einfo "Where <target> is one of the usual kernel targets"
+	einfo ""
+	epause 10
+}