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| author |   Matthew Malcomson <matthew.malcomson@arm.com> | 2019-11-07 17:22:45 +0000 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-11-07 17:23:53 +0000 |
| commit | 1f4cd317b6606fcb2a582a3fc1c1f9437ef7d7b6 (patch) | |
| tree | 49349c1113b4105ee9a03995c03a3fa9f73c31a9 /opcodes/aarch64-tbl.h | |
| parent | [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10] (diff) | |
| download | binutils-gdb-1f4cd317b6606fcb2a582a3fc1c1f9437ef7d7b6.tar.gz binutils-gdb-1f4cd317b6606fcb2a582a3fc1c1f9437ef7d7b6.tar.bz2 binutils-gdb-1f4cd317b6606fcb2a582a3fc1c1f9437ef7d7b6.zip | |
[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]
Hi,
This patch is part of a series that adds support for Armv8.6-A
to binutils.
In this last patch, the new Data Gathering Hint mnemonic is introduced.
Committed on behalf of Mihail Ionescu.
gas/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* testsuite/gas/aarch64/dgh.s: New test.
* testsuite/gas/aarch64/dgh.d: New test.
opcodes/ChangeLog:
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
(aarch64_opcode_table): Add data gathering hint mnemonic.
* opcodes/aarch64-dis-2.c: Account for new instruction.
Is it ok for trunk?
Regards,
Mihail
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3d1a0631886..dc7661a9689 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2557,6 +2557,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve = #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } +#define V8_6_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, ARMV8_6, OPS, QUALS, FLAGS, 0, 0, NULL } #define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL } #define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \ @@ -5072,6 +5074,9 @@ struct aarch64_opcode aarch64_opcode_table[] = V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0), + /* V8.6 instructions */ + V8_6_INSN("dgh", 0xd50320df, 0xffffffff, aarch64_misc, OP0 (), {}, 0), + /* Matrix Multiply instructions. */ INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), |